The present invention relates to a semiconductor memory device, and more particularly to a column redundancy circuit and method of a semiconductor memory device for determining an enable operation of a redundancy column or a normal column under input of a column address.
At present, there are provided in all semiconductor memory devices a redundancy memory cell array and a redundancy circuit for repairing a defective memory cell with a redundancy memory cell. When a redundancy memory cell array is added to a normal memory cell array and an address for designating any one defective memory cell of the normal memory cell arrays is inputted, a redundancy operation is used to select a redundancy row and column connected to the redundancy memory cell by decoding the address inputted. Such an operation is performed by a redundancy decoder. In this case, an output signal of the redundancy circuit for programming the defective address checks whether the normal decoder and the redundancy decoder are enabled or not. As a circuit for programming the defective address, the redundancy circuit programs the defective address by laser cutting according to an address that is input for decoding appropriate fuses included in the redundancy circuit.
The column redundancy circuit determines whether the redundancy column or the normal column is selected or not whenever the column address is inputted. In case that the address designating the defective column address is inputted, the semiconductor memory device is employed to select a redundancy column instead of the defective column.
FIG. 1 is a view showing column redundancy circuit according to a prior art. The column redundancy circuit shown in FIG. 1 is comprised of a controlling circuit 84, a programming part 86, a control signal outputting part 88 for data input fuse, and a redundancy enable control signal outputting part 90. The programming circuit 86 is controlled by an output signal of the controlling circuit 84 and inputs column addresses CAi and CAi (i=0.about.7) to thereby program the column address repaired. The control signal outputting circuit 88 inputs an output signal of the programming circuit 86 and an output signal of a NAND gate 12 of the controlling part 84 and then outputs a control signal .phi. DFP for data input fuse. And, the redundancy enable control signal outputting part 90 outputs a redundancy enable control signal RENi under control of each output signal and a block write signal .PHI. BW of the programming circuit 86.
The controlling circuit 84 is comprised of a PMOS transistor 2, an NMOS transistor 4, a master fuse MF, an inverter 8, a PMOS transistor 6, an inverter 10, a NAND gate 12, and an inverter 14. The PMOS transistor 2 is connected between the power supply voltage VCC and a node N1 to input a control signal .phi. CFP to a gate terminal. The NMOS transistor 4 is connected between the node N1 and the ground voltage VSS to input the control signal .phi. CFP to the gate terminal. The master fuse MF is connected between the node N1 and the NMOS transistor 4 to determine whether the column redundancy circuit is enabled or not. The inverter 8 inputs a signal set at the node N1 and then reverses the signal. The PMOS transistor 6 whose gate terminal is controlled by an output signal of the inverter 6 is connected between the power supply voltage VCC and the node N1. The inverter 10 inputs an output signal of the inverter 8. The NAND gate 12 inputs an output signal of the inverter 10 and a control signal .PHI. CFE. And, the inverter 14 inputs an output signal of the NAND gate 12. At the moment, the control signals .PHI. CFP and .phi. CFE are generated at logic "high" level through a predetermined logic circuit in synchronization with a row address strobe signal RAS before a delay time TRCD (RAS to CAS delay) required until the column address strobe signal CAS is enabled from a time the row address signal strobe signal RAS is enabled. Therefore, such control signals .PHI. CFP and .phi. CFE are maintained at the logic "low" level in a precharge interval of the row address strobe signal RAS.
There are provided in the programming circuit 86 a plurality of transmission gates 16, 18, . . . , 46 and a plurality of fuses fl, f2, . . . ,f16. The plurality of transmission gates whose gate terminals are controlled by the NAND gate 12 and the output signal of the inverter 14 of the controlling circuit 84, input the column addresses CAi and CAi (i=0.about.7) to each one terminal. And, the plurality of fuses are connected to the other terminals of the transmission gates, respectively. In such construction, the two fuses fl and f2 are connected to a node N2 and fused to generate a desired output as described hereafter and the rest of fuse pairs f3, f4, . . . f15, f16 are connected to nodes N3, N4, . . . , N8, N9, respectively.
The control signal outputting circuit 88 for data input fuse has NMOS transistors 48, 50, . . . , 62, and inverters 64 and 66. The NMOS transistors 48, 50, . . . , 62 have gate terminals to which the output signals of the NAND gate 12 of the controlling circuit 84 are inputted, drain terminals connected to the nodes N2, N3, . . ., N9 of the programming circuit 86, and source terminals connected to the ground voltage VSS. The inverter 64 inputs the output signal of the NAND gate 12 of the controlling circuit 84. The inverter 66 inverts an output signal of the inverter 64 to output a control signal .PHI. DFP for data input fuse.
There are provided NAND gates 76, 78, 80, 70, 68 and a NOR gate 72 in the redundancy enable control signal outputting circuit 90. The NAND gate 76 inputs signals of the nodes N2, N3, and N4 and the NAND gate 78 inputs signals of the nodes N5 and N6. The NAND gate 80 inputs signals of the nodes N7, N8, and N9 and the NOR gate 72 inputs output signals of the NAND gates 78 and 80. The NAND gate 70 inputs an output signal of the NAND gate 76 and an output signal of the inverter 74 inputting the block write signal .PHI. BW. And, the NAND gate 68 inputs output signals of the NAND gate 70 and the NOR gate 72 to output the redundancy enable control signal RENi.
The column redundancy circuit shown in FIG. 1 informs that the master fuse MF of the controlling circuit 84 is cut and repaired. Thereafter, the column redundancy circuit cuts the fuses fl, f2, . . . , f16 according to each value of the column addresses CAi and CAi inputted, which are connected to the transmission gates 16, 18, . . . , 46 of the programming circuit 86. In case that the repaired column address CAi is "10011011", the column address CAi is inputted as "01100100" having a complemental logic level against the column address CAi. In this case, the fuse connected to the transmission gate to which the repaired column addresses CAi and CAi are inputted as "1", is cut. That is, in case that the repaired column address CAi is "10011011", the column redundancy circuit shown in FIG. 1 cuts the fuses f1, f4, f6, f7, f9, f12, f13, and f15. At this time, any one of the fuses fl, fl, . . . , f16 connected to the nodes N2, N3, . . . , N9 should be cut.
First of all, the control signals .phi. CFP and .phi. CFE are maintained at the logic "low" level in the precharge interval of the row address strobe signal RAS. In case that the row address strobe signal RAS is maintained at the logic "low" level, if the control signal .PHI. CFP is inputted at the logic "low" level, the PMOS transistor 2 is turned on to set a signal to the node N1 at the logic "high" level. Therefore, a signal set to the logic "high" level and a signal set to the logic "low" level are input to the NAND gate 12, so that a signal set to the logic "high" level is outputted from the NAND gate 12. Thereafter, the signal is outputted at the logic "low" level through the inverter 14 and all the transmission gates 16, 18, . . . , 46 are turned off. Meanwhile, the output signal of the NAND gate 12 is input to the gate terminals of the NMOS transistors 48, 50, . . . , 62 included in the control signal outputting part 88 at the logic "high" level, so that all of the NMOS transistors are turned on.
Again, in case that the row address strobe signal RAS is active, the control signal .PHI. CFP is inputted to the controlling part 84 at the logic "high" level. Thus, the PMOS transistor 2 is turned off. Further, since the PMOS transistor 6 is turned on in the node N1, a signal of the logic "high" level is set. Thereafter, the signal set to the logic "high" level and the control signal .PHI. CFE set to the logic "high" level are inputted to the NAND gate 12, so that an output signal set to the logic "low" level is outputted from the NAND gate 12. Therefore, the signal is outputted at the logic "high" level through the inverter 14 and all of the transmission gates 16, 18, . . ., 46 are thus turned on. And, the NMOS transistors 48, 50, . . . , 62 included in the control signal outputting part 88 are turned off. The block write signal .phi. BW inputted to the inverter 74 of the redundancy enable control signal outputting circuit 90 is at the logic "high" level during the block writing. If the block write signal .phi. BW performs a 8-bits-block write operation, the column addresses CA0 to CA2 perform a "Don't Care" operation. At the time, data DQ0, DQ1, . . . , DQ7 inputted from a data input buffer perform the functions instead of the column addresses CA0 to CA2.
FIG. 2 is a view showing a redundancy column select circuit according to a prior art. The redundancy column select circuit is composed of an inputting circuit 112 for inputting data inputted from the data input buffer and an outputting circuit 114 for generating a redundancy column select signal RCSL. There are provided in the inputting part 112 NMOS transistors NT1, NT2, . . . , NT8 and a PMOS transistor 92. One terminal of each of the NMOS transistors NT1, NT2, . . . , NT8 is connected to the data DQ0, DQ1, . . . , DQ7 and the other terminal thereof is each connected to the fuses f17, f18, . . . , 124. Further, gate terminals of the NMOS transistors are connected to the power supply voltage VCC. The PMOS transistor 92 whose gate terminal is connected to an output signal of an inverter 110 is connected between the power supply voltage VCC and a node N10, the inverter 110 inputting the signal .PHI. DFP.
Also, there are provided in the outputting circuit 114 an inverter 96, a PMOS transistor 94, a NAND gate 98, a NAND gate 100, an inverter 104, a NAND gate 106, and an inverter 108. The inverter 96 reverses a signal set at the node N10. The PMOS transistor 94 whose gate terminal is controlled by the inverter 96 is connected between the power supply voltage VCC and the node N10. The NAND gate 98 inputs the block write signal .phi. BW and the output signal of the inverter 96. The NAND gate 100 inputs an output signal of the NAND gate 98 and an output signal of the inverter 102 inputting the redundancy enable control signal RENi. The inverter 104 reverses an output signal of the NAND gate 100. The NAND gate 106 inputs an output signal of the inverter 104 and control signals .PHI. YE and .phi. CP. And, the inverter 108 inputs an output signal of the NAND gate 106 to generate the redundancy column select signal RCSL.
As shown in FIG. 2, there are provided in the inputting circuit 112 NMOS transistors NT1, NT2, . . . , NT8 and a PMOS transistor 92. One terminal of each of the NMOS transistors NT1, NT2, . . . , NT8 is connected to the data DQ0, DQ1, . . . , DQ7 and the other terminal thereof is each connected to the fuses f17, f18, . . . , f24. Further, gate terminals of the NMOS transistors are connected to the power supply voltage VCC. The PMOS transistor 92 whose gate terminal is connected to an output signal of an inverter 110 is connected between the power supply voltage VCC and the node N10, the inverter 110 inputting the signal .PHI. DFP. Such a construction is employed to connect the data input fuses f17, f18, . . . , f24 in order to code the redundancy column select signal RCSL. Thereafter, it is possible to code the redundancy column select signal RCSL under use of any one data selected by cutting all of the data input fuses except the one data input fuse corresponding to the data of interest. At the moment, the control signals .phi. CP and .phi. YE function as important signals determining a time the redundancy column select signal RCSL is enabled. That is, the control signal .PHI. YE is developed as a value of cell data on a bit line to thereby inform that the redundancy column select signal will be enabled. Also, the other control signal .phi. CP enables the redundancy column select signal after going by a predetermined time from the time the column address CAi was received.
As mentioned above, the conventional column redundancy circuit, as shown in FIG. 1, should cut any one of the fuses connected to the nodes N2, N3, . . ., N9 to thereby use it. Accordingly, there should be provided double fuse, except the master fuse MF, in comparison with the number of column addresses used in decoding the column. That is, in case that one fuse corresponding to the column address CAi is cut, it is not necessary to cut the other fuse corresponding to the other column address CAi. Therefore, this means that the fuses should be more used than the number of fuses required in obtaining information to be desired. This results in increasing the total dimension of a chip and making a process difficult in that the fuse is selectively cut.
Further, as shown in FIG. 2, in case that the data input fuse is used to control a block write function to be generally used in a graphic memory, there arises an outstanding increase in the number of fuses because the column redundancy circuit shown in FIG. 1 does not memorize various uses for the column address for enabling the redundancy column select signal RCSL. Also, in the prior art, there arises a problem in that the dimension of the chip is increased due to use of the data input fuse. Therefore, a desirable method is to input data to the data input buffer without using the data input fuse, thereby coding the redundancy column select signal.